Global (United States, European Union and China)
FinFET Technology Major Applications/End users: Smartphones, Computers and Tablets, Wearables, High-End Networks & Automotive
There are two main configurations of
FinFET devices as shown in Figure 1.
Zhang, "Performance fluctuation of
FinFETs with Schottky barrier source/drain," IEEE Electron Device Letters, vol.
(4.) Tang, H., et al., "Diagnosing Cell Internal Defects for
FinFET Technology," Poster, IEEE International Test Conference, 2016.
To get better results of low power consumption, delay and power delay product using CMOS 65 nm technology instead of
FINFET 32 nm technology is used.
The optimal configuration of a pass transistor logic (PTL) full adder cell based on four-terminal
FinFET is shown in Figure 7.
In work led by Peide Ye, an associate professor of electrical and computer engineering, the Purdue researchers are the first to create
finFETs using a technology called atomic layer deposition.
Multi-gate MOSFET or
FinFET happens to be better replacement for CMOS for scaling beyond sub-micron regime [1].