MIC

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MIC

MIC

Abbreviation for:
maternal and infant care
medical industrial complex
medical intensive care (intensive care)
methyl isocyanate
microscopy (see there)
minimum inhibitory concentration (see there)
mobile intensive care
model immune complex
morphology-immunology-cytogenetics (haematology)

MIC

1. Methyl isocyanate.

MIC

Abbreviation for minimal inhibitory concentration.
References in periodicals archive ?
Timing results for used algorithm on targets CPu architectures Intel Multi-core Intel Many Integrated Core Platform Xeon Phi Architecture Knights Knights Test (Monte Carlo) Haswell (HSW) Corner (KNC) Landing (KNL) Performance time [ms] 1.
Furumura, "Performance optimization of the 3D FDM simulation of seismic wave propagation on the Intel Xeon Phi coprocessor using the ppOpen-APPL/FDM library," Lecture Notes in Computer Science, vol.
The 180 new bullx B515 compute nodes will each include two Intel Xeon Phi coprocessors delivering an additional 400 Teraflops, taking the total power of the Helios system to almost 2 Petaflops.
# Monthly rates comprise of (24 cores and 2 Xeon Phi) for 30 days
The first Xeon Phi chips will be used alongside Intel's Xeon E5 server CPUs in a 10-petaflop supercomputer called Stampede that could be active at Texas Advanced Computing Center (TACC) at the University of Texas by early next year.
As a bootable x86 CPU, the Intel Xeon Phi processor scales efficiently without being constrained by a dependency on the PCIe bus like GPU accelerators.
blocked high-end processors, such as Intel's Xeon Phi chips, from being sold to a number of Chinese supercomputing centers.
Also, ECMWF will also receive additional Cray Sonexion 2000 scale-out Lustre storage, and a 32-node Cray XC40-AC system with the next-generation of the Intel Xeon Phi processor code-named 'Knights Landing'.
The large cluster, which will be put into operation in 2015, will be among the 50 largest supercomputers in the world, and will become the largest Intel (NASDAQ: INTC) Xeon Phi coprocessor-based cluster in Europe.
The objectives of the code are to achieve scalability to very large numbers of compute nodes, larger than what is currently possible; and heterogeneous CPU-Intel Xeon Phi computation.
Intel offers a supercomputing mega-chip called Xeon Phi 7290 with 72 cores as a primary chip, but it does not integrate a GPU.