- Capability to use the MIPI M-PHY
v4.1 transmission mode known as High Speed GEAR 4 to achieve 11.6 gigabits per second (Gbps) data rates per lanea 2x performance increase over the previous (v1.61) specification.
"Automated serial test solutions such as what Tektronix is now offering for MIPI M-PHY
3.1 allow engineers to complete the full set of tests in significantly less time while improving consistency.
The new MIPI M-PHY
serial interface presents some significant challenges for oscilloscope measurements and probing, including minimising common mode loading on the device under test (DUT) and signal fidelity requirements such as wide bandwidth, low noise, and high sensitivity.
Electronic design automation specialist Synopsys Inc (Nasdaq:SNPS) announced on Wednesday the availability of a new DesignWare MIPI M-PHY
IP solution supporting multiple speed gears and a wide range of high-speed interfaces for mobile applications.
Our silicon-proven DesignWare[R] IP supporting the MIPI UniPro, MIPI M-PHY
and JEDEC UFS standards enables designers to achieve the stringent power, bandwidth and latency requirements of mobile SoCs utilizing the UniPort-M interface for chip-to-chip communication.
"As a longtime member and supporter of the MIPI Alliance, Synopsys continues to offer IP that supports the rapidly evolving mobile market, including an LLI-compliant DesignWare(R) MIPI M-PHY
IP solution with high data rates and low power consumption to enable highly competitive, future-proof designs."
The companies added that the joint solution, available now for select early access customers, consists of Arteris' Flex LLI MIPI LLI digital controller IP and Synopsys' DesignWare MIPI M-PHY
MIPI Alliance, an international organization that develops interface specifications for mobile and mobile-influenced industries, has announced an updated version of its MIPI M-PHY
specification, a physical-layer interface that supports chip-to-chip and multimedia protocols and applications.
LeCroy will be demonstrating the MIPI M-PHY
test suite using the silicon-proven Mixel M-PHY at the MIPI Alliance Test Forum Days meeting in Copenhagen, Denmark,
Multilevel modulation schemes, USB 3.1, DDR4/LPDDR4, and MIPI M-PHY
are specific areas of focus while issues to be addressed include signal integrity and jitter as well as physical-layer (PHY) characterization, protocol variations, and compliance.