The TSVM is divided into two structures: the TSVM cache (TC), which works as a L1 cache
for synchronization variables, and a conventional memory.
93 GHz, 64 KB L1 cache
and 256 KB L2 cache per core, 8 MB L3 cache per processor, 48 GB main memory, running Solaris 10, Oracle 10g and SAP enhancement package 4 for SAP ERP 6.
0 GHz, 32 KB L1 cache
per core, 4 MB L2 cache shared per 2 cores and 32 GB main memory.
52 GHZ, 64 KB (D) + 64 KB (1) L1 cache
per core, 6 MB L2 cache per processor, 1024 GB main memory, running Solaris 10, Oracle Database 10g and SAP ERP 6.
According to Peleg Aviely, Plurality's vice president of engineering, "The Technion is very interested in our implementation of shared L1 cache
memory, whose traits are reminiscent of a Parallel Random Access Machine (PRAM), and in our hardware synchronizer/scheduler, which lets the programmer focus on concurrency instead of synchronization and communication issues.
0 GHz), 32 KB L1 cache
, 4 MB L2 cache and 32 GB main memory.
As a synthesizable version of IBM's PowerPC 464 hard core, the PowerPC 460S allows the system-on-chip (SoC) designer to select the L2 cache size, L1 cache
size, and multi-core processor local bus necessary to optimize their design.
6 GHz, 32 KB L1 cache
, 256 KB L2 cache, 9 MB L3 cache, 256 GB main memory; 180 DLG/UPD servers: HP Integrity Model rx4640, 4-way SMP, Intel Itanium 2, 1.
0 GHz), 2x28 KB L1 cache
, 2x2 MB L2 cache, and 32 GB main memory.
The 32 kBytes L1 cache
includes a parity check for both tags and data, while the 512 kBytes L2 cache provides a parity check on tags and ECC protection on data.