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Therefore, we should give priority to the L1 cache and first choose the L1 displacement that minimizes the estimated cost of L1 conflicts, using the same search algorithm described in Section 4.
The most important area of concern is the bank conflicts in the L1 cache.
It runs at 300, 333, 350, 366, 380, 400, or 450 MHz and includes 32-K instruction and 32-K data L1 caches.
It is a Pentium-class CPU with an x86-native instruction set and 32KB of integrated L1 cache that efficiently runs Windows([R]) CE, Windows([R])XP embedded, Linux, and other x86-compatible operating systems such as VxWorks and QNX.
0 GHz, 32 KB L1 cache per core, 4 MB L2 cache shared per 2 cores and 32 GB main memory.
0 GHz), 32 KB L1 cache, 4 MB L2 cache and 32 GB main memory.
6 GHz, 32 KB L1 cache, 256 KB L2 cache, 9 MB L3 cache, 256 GB main memory; 180 DLG/UPD servers: HP Integrity Model rx4640, 4-way SMP, Intel Itanium 2, 1.
0 GHz), 2x28 KB L1 cache, 2x2 MB L2 cache, and 32 GB main memory.
The MPC7448 and MPC8641D share many architectural similarities that make them highly compatible, including support for asymmetric and symmetric multiprocessing, identical 32KB L1 cache and 1MB L2 cache, and identical AltiVec technology attributes and performance.
We have speculated that VIA would be better off pursuing the IDT WinChip 4 processor design rather than the Cyrix cores it has acquired, although Cyrix's brand name and bus interface designs, among other Cyrix assets, are also valuable," he said, "the WinChip 4 design uses large L1 caches (128K total) and no L2 caches, a strategy that sets it apart from Intel and Cyrix, which use smaller L1 caches (32K total) coupled with separate, larger L2 caches (256K) on their newest chip designs.
Both Flash and SRAM have on-chip L1 caches to further speed processing.