Therefore, we should give priority to the L1 cache
and first choose the L1 displacement that minimizes the estimated cost of L1 conflicts, using the same search algorithm described in Section 4.
It runs at 300, 333, 350, 366, 380, 400, or 450 MHz and includes 32-K instruction and 32-K data L1 caches
We have speculated that VIA would be better off pursuing the IDT WinChip 4 processor design rather than the Cyrix cores it has acquired, although Cyrix's brand name and bus interface designs, among other Cyrix assets, are also valuable," he said, "the WinChip 4 design uses large L1 caches
(128K total) and no L2 caches, a strategy that sets it apart from Intel and Cyrix, which use smaller L1 caches
(32K total) coupled with separate, larger L2 caches (256K) on their newest chip designs.