cache

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cache

 [kash]
a memory mechanism used by a computer to accelerate access to information.

cache

A storage area on a PC’s hard drive where the browser temporarily stores web pages and/or graphic elements.
References in periodicals archive ?
Especially, it allows us to count the cache misses in our algorithms.
The coverage factor is the fraction of original cache misses that are prefetched.
Smith found that tagged prefetching reduces cache miss ratios in a unified (both instruction and data) cache by between 50% and 90% for a set of trace-driven simulations.
The instruction cache miss rate changed from 3.8% for the first layout to 5.4% for the second layout; this is a remarkable change for such a trivial difference between the layouts.
The most dominant QoS parameter, packet loss rate (PLR) in a router is encountered in system activities that may arise due to different errors like deadline miss, L1 and L2 cache misses, page fault, etc.
Meanwhile, high cache miss rate depends on the size of the cache and the efficiency of the replacement policy engaged in the cache management.
First, in Section 2 we depict several proposals aimed at reducing the cache miss latency.
Direct cache-miss measurements indicate that the difference in performance is largely due to differences in the number of level-2 cache misses that the two algorithms generate.
Adding more memory to the server does reduce the cache miss rate, but adding enough memory to achieve a significant effect is prohibitively expensive.
But the net effect on performance will depend both on improvements due to better branch prediction and on penalties due to worse cache miss rates.
Some problems with embedding DRAM on logic include bandwidth constraints and providing access to embedded DRAM after a cache miss. NEC Corp and Hitachi Ltd have each outlined plans to provide embedded DRAM processes and ways to overcome these problems.
Real machines are typically designed to achieve a constant throughput at each level of the memory hierarchy, yielding a constant per-element latency for a cache miss. In the cache model, this translates to a constant cache miss latency at each level.