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The bit cell charge is important because, over time, charge leaks from a programmed cell.
The problem for the IC test engineer is that, although these fast bits might work properly when the EEPROM is initially programmed and erased, after multiple cycles, the low programming voltage will result in the bit cell failing prematurely.
As shown above, characterization of an EEPROM die calls for measurements of input voltage and bit cell charge.
This DFT method guarantees that every bit cell in every chip in every wafer will be tested with the same input voltage.
After this data-retention bake, the dies were tested to check for drift in the bit cell current.
Automotive quality requirements, however, call for zero defects in any bit cells in any EEPROM device.
This DFT circuitry connects the on-chip high-voltage generator in such a way that the voltage needed to program and erase the bit cells may be driven from outside the chip.
Once all bit cells have been programmed or erased, a digital check can be initialized by sourcing an external reference current to the external test-mode pin.