RISC

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Related to reduced instruction set computing: complex instruction set computing, Instruction set architecture

RISC

Cardiology A clinical trial–Risk of Myocardial Infarction & Death by Treatment with Low Dose Aspirin & Intravenous Heparin in Men with Unstable Coronary Artery Disease that evaluated the risk of MI and death during therapy with low-dose aspirin and IV heparin in high-risk men. See Acute myocardial infarction, Low-dose aspirin.
References in periodicals archive ?
The high-performance smart card is the first in the industry to provide a 32-bit Reduced Instruction Set Computing (RISC) microprocessor and the first to provide a hardware-based Secure Memory Management Unit (SMU) for securely separating multi-applications.
Pyramid's systems are based on a symmetric multiprocessing architecture that combines an enhanced UNIX(R) operating system with reduced instruction set computing (RISC) technology.
Microware's OS-9 real-time operating system (RTOS) now fully supports microprocessors using ARM's reduced instruction set computing (RISC) intellectual property for portable devices, multimedia and embedded applications.
MIPS Technologies designs and licenses high-performance 32- and 64- bit reduced instruction set computing (RISC) intellectual property for the digital consumer and high-end control-oriented embedded markets.

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