The hard macro implementations include ARM AMBA[R]-compliant high performance system components to maximize data traffic speed and minimize power consumption and silicon area.
Both ARM dual core Cortex-A9 hard macros will share a common seven-power domain, dual-NEON[TM] technology configuration supporting SMP (symmetrical multiprocessing) operating systems with up to 8MB of Level2 cache memory and will be delivered with all scripts, vectors and libraries required to integrate the macro directly within any SoC device.
To enable the development of high-efficiency, low risk SoCs using other Cortex-A9 processor configurations, ARM also provides the silicon-proven SoC-level ARM Physical IP platform used to build these hard macros, and a range of AMBA-compliant system development components and tools.
In addition, the ARM Active Assist consulting service, developed in conjunction with the hard macros, enables ARM Partners to efficiently integrate the hardened macro into their SoC design to realize maximum system performance with lowest risk and fastest time-to-market.
It can take designs with multiple millions of placeable instances and hundreds of hard macros
, and create a high-quality placement in a matter of hours for the entire chip.
Many complex designs consist of hundreds of hard macros
ARM will use these high-performance, silicon proven PLL hard macros to provide the reliable, high frequency and low-jitter clocks required for these advanced, scalable and high functionality applications processors.
These high quality, low-jitter PLL and DLL hard macros are suited to a wide variety of interface standards and chip applications.
The hard macros are available for a per use license fee and no royalty fees.
The superior signal integrity of the HSTL I/Os combined with the timing-closed hard macros
allow customers to rapidly design their ASICs and unlock the performance benefits of low-latency, high bandwidth RLDRAM and FCRAM memories at a reduced risk.
TCI), a leading provider of analog and mixed-signal intellectual property (IP) for the semiconductor, systems and electronics industries announced today the immediate availability of a new line of silicon-proven General Purpose Phase-Locked Loop (PLL) hard macros
that are well suited for system clock, DDR and general purpose timing applications.
Ciranova Helix is a plug-and-play solution that works in any OpenAccess-based design flow to accelerate and improve predictability in custom IC layout; it works with a variety of libraries including parameterized cells (PCells), TSMC Analog Base Cells[TM], standard cells, and hard macros