The Cortex-A9 power-optimized hard macro implementation delivers its peak performance of 4000 DMIPS while consuming less than 250mW per CPU when selected from typical silicon.
The hard macro implementations include ARM AMBA[R]-compliant high performance system components to maximize data traffic speed and minimize power consumption and silicon area.
Both ARM dual core Cortex-A9 hard macros will share a common seven-power domain, dual-NEON[TM] technology configuration supporting SMP (symmetrical multiprocessing) operating systems with up to 8MB of Level2 cache memory and will be delivered with all scripts, vectors and libraries required to integrate the macro directly within any SoC device.
To enable the development of high-efficiency, low risk SoCs using other Cortex-A9 processor configurations, ARM also provides the silicon-proven SoC-level ARM Physical IP platform used to build these hard macros, and a range of AMBA-compliant system development components and tools.
In addition, the ARM Active Assist consulting service, developed in conjunction with the hard macros, enables ARM Partners to efficiently integrate the hardened macro into their SoC design to realize maximum system performance with lowest risk and fastest time-to-market.
The hard macros are available for a per use license fee and no royalty fees.
True Circuits develops and markets a broad range of industry leading PLLs, DLLs and other mixed-signal hard macros for ICs for the semiconductor, systems and electronics industries.