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BUS

Abbreviation for Bartholin glands, urethra, Skene glands.

bus

a set of parallel wires in a computer to which the central processing unit and all input-output units are connected. Each separate wire carries the electric current representing 1 bit. Buses interconnect the parts of the computer that communicate with each other, such as a video card or modem.

bus

The hardware that controls the flow of commands between the main processor and other components—memory, peripherals, etc.

BUS

Abbreviation for:
Bartholin's, urethral, Skene's (glands)
biological units
buspirone
busulfan, see there
References in periodicals archive ?
PCIe uses a dual simplex serial data stream with an embedded clock to overcome many of the performance limitations of parallel bus architectures.
SERIAL BUS ARCHITECTURE: Ultra ATA Bus Architecture
It is incumbent on the system integrator or designer to select equipment, which will properly interface with all the nodes on the bus given a specific bus architecture.
With the new service bus architecture and open interfaces, our customers can now begin to provision data to other areas of the organization.
Bus converter modules, which convert a 48V bus to a 12V rail for intermediate bus architecture applications and other isolated converters operating from 24V and 48V busses are included.
The controller supports the fast 133 MHz 64bit PCI-X bus architecture to deliver maximum data throughput of 3 Gbits/sec per port.
Nasdaq:PWER) announced that their Z-One(TM) Digital Intermediate Bus Architecture (IBA) has won EDN Magazine's 2004 Innovation of the Year Award.
These applications implement distributed power architecture (DPA) and intermediate bus architecture (IBA) systems -- that use more DC-DC converters -- in place of the AC-DC units.
An advantage of SATA's point-to-point architecture over bus architectures (such as SCSI) is that a unique cable provides connectivity to each drive.
All PCI-based architectures, also know as "shared bus architectures," are able to handle communications with only one device at any given time, creating contention between network devices.
Other bus architectures, such as Mercury's Race and Sky's Skychannel, offer good performance but are not scaleable to the levels of RapidIO.
CoWare technologies have been offering solutions to a number of design challenges, such as creating custom processors and processor models with LISATek(TM); defining and evaluating digital signal processing algorithms with SPW; and modeling complex logic functions such as bus architectures and peripheral IP blocks using ConvergenSC(R).