MIC

(redirected from Xeon Phi)
Also found in: Dictionary, Thesaurus, Financial, Encyclopedia.

MIC

MIC

MIC

Abbreviation for:
maternal and infant care
medical industrial complex
medical intensive care (intensive care)
methyl isocyanate
microscopy (see there)
minimum inhibitory concentration (see there)
mobile intensive care
model immune complex
morphology-immunology-cytogenetics (haematology)

MIC

1. Methyl isocyanate.

MIC

Abbreviation for minimal inhibitory concentration.

MIC,

n an abbreviation for minimal inhibitory concentration, the lowest concentration of an antibiotic that is needed to hinder the growth of bacteria.

MIC

minimal inhibitory concentration.
References in periodicals archive ?
The Intel Xeon Phi range of coprocessors has been designed with this in mind, and we are very pleased that the Helios supercomputer will be benefiting from this," explained Stephane Negre, CEO of Intel France and Regional Manager of Intel Western Europe.
The first Xeon Phi chips will be used alongside Intel's Xeon E5 server CPUs in a 10-petaflop supercomputer called Stampede that could be active at Texas Advanced Computing Center (TACC) at the University of Texas by early next year.
Across a wide range of applications and environments - from machine learning to high performance computing (HPC), the Intel Xeon Phi product family helps solve the biggest computational challenges faster and with greater efficiency and scale3.
It will feature 864 Intel Xeon Phi 7120 coprocessors cards with 52,704 cores and 13.
With each node comprising two Intel Xeon CPUs and three Xeon Phi coprocessors, the computations used more than 1.
Param Yuva 2 has 221 Intel Xeon E5-2670 nodes that also consist of Intel Xeon Phi 5110P, with Linux 64-bit (CentOS 6.
As usage expands, hopefully PC makers and other partners will sign on to sell Xeon Phi desktops, said Charles Wuischpard, general manager of the HPC Platform Group at Intel, PCworld reported.
The Theta system will be powered by Intel Xeon processors and next-generation Intel Xeon Phi processors, code-named Knights Landing, and will be based on the next-generation Cray XC supercomputer.
The large cluster, which will be put into operation in 2015, will be among the 50 largest supercomputers in the world and will become the largest Intel Xeon Phi coprocessor-based cluster in Europe.
In particular, it is far too easy to become lost in the minutia of writing code that can run efficiently on NVIDIA GPUs, AMD GPUs, x86, ARM and Intel Xeon Phi while also addressing the numerous compiler and user interface vagaries to compile and create user interfaces for Linux, OS X, Windows, iOS and Android devices.
Xeon IvyBridge processors and three Xeon Phi co-processors for a combined total
The new system will be powered by a combination of current 32nm Xeon E5 processors and future 22nm Ivy Bridge processors, together with around 600 Xeon Phi co-processors (based on Intel's MIC architecture), running inside HP ProLiant Gen 8 servers.