integrated circuit

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integrated circuit

a circuit, such as a computer chip, whose components are fabricated on a single semiconductor substrate.
References in periodicals archive ?
For comparison, FIGURE 7 illustrates the "after" "optimized" board, with improvements achieved by simply re-mapping the pinouts of U2 without changing the performance of the silicon die.
The pin count reduction afforded by serial links reduces system cost through smaller silicon die size, lower pin count packages and less expensive connectors and cables.
It offers an integration of a MEMS accelerometer and a control IC in one silicon die.
By integrating multiple silicon die in a single package, we are able to deliver the Virtex-7 2000T device - the world's highest capacity FPGA.
Offering a low-cost, highly flexible alternative to traditional ceramic and over molded packaging options, RJR's LCP air cavity packaging technology delivers a high degree of electrical isolation to the silicon die in a modular assembly process that supports the use of various thermally-enhanced interchangeable bases.
LinkSwitch-PL, like its isolated counterpart LinkSwitch-PH, incorporates the controller and high-voltage power MOSFET into a single silicon die, simplifying PCB layout by further minimizing component count and eliminating parasitics between the controller and high-voltage power MOSFET.
This results in outstanding RDS(ON) per silicon die area, enabling physically small components to achieve ultra-low on-state losses.
In addition, the paper explores solutions for optimal designs in terms of power performance and silicon die area.
Our focus on complete solutions linked to the application ecosystem, delivered with the lowest power consumption and smallest silicon die size is an ideal match for Chipsbank's requirements," said Wei-Jin Dai, President and CEO of Vivante Corporation.
Both IC families are monolithic - incorporating the controller and MOSFET onto a single silicon die - which simplifies PCB layout by minimizing component count and eliminating parasitics between the controller and power MOSFET.
At such speeds, a thorough signal integrity analysis of the entire system comprising the SoC silicon die, SoC package, printed circuit board, and the SDRAM is critical to validate the channel robustness under worst case operating conditions.