2] N bits, the latter does not use any bit and always sends N-1 coherence messages (invalidations or cache-to-cache transfer requests) when the home node cannot directly satisfy a certain cache miss
a shows the average cache miss
rate for all combinations of two different benchmarks in three situations: executing one thread and then the other (Sngl: single-thread), multithreaded execution with split caches (Sp), and multithreaded execution with a shared cache (Sh).
For most embedded systems, the cache miss
rate is even bigger than 1%.
Customer Benchmark Showed 80% Reduction in Cache Miss
Rate and Dramatic
The ARM10TDMI core employs parallel instruction execution, branch prediction, and the ability to continue executing in the presence of a cache miss
to achieve high performance on real applications.